A programmable resistive device in a programmable resistive memory is generally referred to a device's resistance states that may change after means of programming. Resistance states can also be determined by resistance values. For example, a resistive device can be a One-Time Programmable (OTP) device, such as electrical fuse, and the programming means can apply a high voltage to induce a high current to flow through the OTP element. When a high current flows through an OTP element by turning on a program selector, the OTP element can be programmed, or burned into a high or low resistance state (depending on either fuse or anti-fuse).
An electrical fuse is a common OTP which is a programmable resistive device that can be constructed from a segment of interconnect, such as polysilicon, silicided polysilicon, silicide, metal, metal alloy, or some combination thereof. The metal can be aluminum, copper, other transition metals, or non-aluminum metal gate for CMOS. One of the most commonly used electrical fuses is a CMOS gate, fabricated in silicided polysilicon, used as interconnect. The electrical fuse can also be one or more contacts or vias instead of a segment of interconnect. A high current may blow the contact(s) or via(s) into a very high resistance state. The OTP can be an anti-fuse, where a high voltage makes the resistance lower, instead of higher. The anti-fuse can consist of one or more contacts or vias with an insulator in between. The anti-fuse can also be a CMOS gate coupled to a CMOS body with a thin gate oxide as insulator.
The programmable resistive device can be a reversible resistive device that can be programmed into a digital logic value “0” or “1” repetitively and reversibly. The programmable resistive device can be fabricated from phase change material, such as Germanium(Ge), Antimony(Sb), and Tellurium(Te) with composition Ge2Sb2Te5 (GST-225) or GeSbTe-like materials including compositions of Indium (In), Tin (Sn), or Selenium (Se). The phase change material can be programmed into a high resistance amorphous state or a low resistance crystalline state by applying a short and high voltage pulse or a long and low voltage pulse, respectively. The reversible resistive device can be a Resistive RAM (RRAM) with cells fabricated from metal oxides between electrodes, such as Pt/NiO/Pt, TiN/TiOx/HfO2/TiN, TiN/ZnO/Pt. The resistance states can be changed reversibly and determined by polarity, magnitude, duration, or voltage/current-limit of pulse(s) to generate or annihilate conductive filaments. Another programmable resistive device similar to RRAM is a Conductive Bridge RAM (CBRAM) that is based on electro-chemical deposition and removal of metal ions in a thin solid-state electrolyte film. The electrodes can be an oxidizable anode and an inert cathode and the electrolyte can be Ag- or Cu-doped chalcogenide glass such as GeSe or GeS, etc. The resistance states can be changed reversibly and determined by polarity, magnitude, duration, or voltage/current-limit of pulse(s) to generate or annihilate conductive bridges. The programmable resistive device can be an MRAM (Magnetic RAM) with cells fabricated from magnetic multi-layer stacks that construct a Magnetic Tunnel Junction (MTJ). In a Spin Transfer Torque MRAM (STT-MRAM) the direction of currents applied to an MTJ determines parallel or anti-parallel states, and hence low or high resistance states.
A conventional programmable resistive memory cell is shown in FIG. 1. The cell 10 consists of a resistive element 11 and an NMOS program selector 12. The resistive element 11 is coupled to the drain of the NMOS 12 at one end, and to a positive voltage V+ at the other end. The gate of the NMOS 12 is coupled to a select signal (Sel), and the source is coupled to a negative voltage V−. When a high voltage is applied to V+ and a low voltage to V−, the resistive device 10 can be programmed by raising the select signal (Sel) to turn on the NMOS 12. One of the most common resistive elements is a silicided polysilicon, the same material and fabricated at the same time as a MOS gate. The size of the NMOS 12, as program selector, needs to be large enough to deliver the required program current for a few microseconds. The program current for a silicided polysilicon is normally between a few milliamps for a fuse with width of 40 nm to about 20 mA for a fuse with width about 0.6 um. As a result, the cell size of an electrical fuse using silicided polysilicon tends to be very large. The programmable resistive memory cell 10 can be organized as a two-dimensional array with all V+'s in the same column coupled together as bitlines (BLs) and all Sel's in the same row coupled together as wordlines (WLs).
Another programmable resistive memory cell 15 is shown in FIG. 1(b). The programmable resistive memory cell has a programmable resistive element 16 and a diode 17 as program selector. The programmable resistive element 16 is coupled between an anode of the diode 17 and a high voltage V+. A cathode of the diode 17 is coupled to a low voltage V−. By applying a proper voltage between V+ and V− for a proper duration of time, the programmable resistive element 16 can be programmed into high or low resistance states, depending on voltage/current and duration. The diode 17 can be a junction diode constructed from a P+ active region on N well and an N+ active region on the same N well as the P and N terminals of a diode, respectively. In another embodiment, the diode 17 can be a diode constructed from a polysilicon structure with two ends implanted by P+ and N+, respectively. The P or N terminal of either junction diode or polysilicon diode can be implanted by the same source or drain implant in CMOS devices. Either the junction diode or polysilicon diode can be built in standard CMOS processes without any additional masks or process steps. The programmable resistive memory cell 15 can be organized as a two-dimensional array with all V+'s in the same column coupled together as bitlines (BLs) and all Sel's in the same row coupled together as wordline bars (WLBs).
Non-volatile memory (NVM) or programmable resistive memory needs to be protected from unauthorized uses, alternations, or inspections, including read or program. FIG. 2 shows a portion of a block diagram of a Micro-Controller Unit (MCU) 20 embedded with flash memory as in Spansion's STR91xFA. The MCU has a flash memory array 21, control logic 22, and an OTP sector 23. The OTP sector 23 has a P-bit and E-bit, which can AND with the Program enable (PE) and Erase enable (EE) generated from the control logic 22 through gates 24 and 25, respectively, to control the PgmEN and EraEN of the flash memory array 21. The data protection bits are built in OTP, which is a different memory from the flash memory array.
Not only NVMs need to be data protected, OTP memories, either stand alone or embedded, needs to be data protected too. And the protection bits and main array do not have to be different kinds of memories. In general, any programmable resistive memory needs to be protected from unauthorized uses, alternations, or inspections, such as read or program. Hence there is a need for inventing more general data-protection mechanisms for programmable resistive memories, such as one-time-programmable (OTP), multiple-time programmable (MTP), or reversible programmable memories such as PCRAM, RRAM, CBRAM, or MRAM, etc.